Table 7.4 List Of On-Chip Module Interrupts To Dmac - Renesas H8SX/1500 Series Hardware Manual

Table 7.4 List of On-chip module interrupts to DMAC
On-Chip Module Interrupt Source
ADI0 (A/D conversion end interrupt)
ADI1 (A/D conversion end interrupt)
TGI0A (TGI0A input capture/compare match)
TGI1A (TGI1A input capture/compare match)
TGI2A (TGI2A input capture/compare match)
TGI3A (TGI3A input capture/compare match)
RXI3 (receive data full interrupt for SCI channel 3)
TXI3 (transmit data empty interrupt for SCI channel 3)
RXI4 (receive data full interrupt for SCI channel 4)
TXI4 (transmit data empty interrupt for SCI channel 4)
TGI6A (TGI6A input capture/compare match)
TGI7A (TGI7A input capture/compare match)
TGI8A (TGI8A input capture/compare match)
TGI9A (TGI9A input capture/compare match)
TGI10A (TGI10A input capture/compare match)
TGI11A (TGI11A input capture/compare match)
RM0 (message reception in Mailbox 0)
SSRXI0 (receive data full interrupt for SSU channel 0)
SSTXI0 (transmit data empty interrupt or transmit end for SSU channel 0) SSU_0
SSRXI1 (receive data full interrupt for SSU channel 1)
SSTXI1 (transmit data empty interrupt or transmit end for SSU channel 1) SSU_1
SSRXI2 (receive data full interrupt for SSU channel 2)
SSTXI2 (transmit data empty interrupt or transmit end for SSU channel 2) SSU_2
Section 7 DMA Controller (DMAC)
On-Chip
Module
A/D_0
A/D_1
TPU_0
TPU_1
TPU_2
TPU_3
SCI_3
SCI_3
SCI_4
SCI_4
TPU_6
TPU_7
TPU_8
TPU_9
TPU_10
TPU_11
HCAN
SSU_0
SSU_1
SSU_2
Rev. 3.00 Mar. 14, 2006 Page 167 of 804
REJ09B0104-0300
DMRSR
(Vector
Number)
86
87
88
93
97
101
157
158
161
162
164
169
173
177
182
188
221
228
229
232
233
236
237