Figure 9.1 Block Diagram Of Tpu (Unit 0) - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer
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Section 9 16-Bit Timer Pulse Unit (TPU)
Input/output pins
Channel 3:
Channel 4:
Channel 5:
Clock input
Internal clock:
External clock:
Input/output pins
Channel 0:
Channel 1:
Channel 2:
[Legend]
TSTR:
Timer start register
TSYR:
Timer synchronous register
TCR:
Timer control register
TMDR:
Timer mode register
TIOR (H, L): Timer I/O control registers (H, L)
Note: * The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5.
Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at an input capture input and a
compare match cannot be output.
Rev. 3.00 Mar. 14, 2006 Page 256 of 804
REJ09B0104-0300
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TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4*
TIOCB4*
TIOCA5*
TIOCB5*
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
Pφ/4096
TCLKA
TCLKB
TCLKC
TCLKD
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2

Figure 9.1 Block Diagram of TPU (Unit 0)

TIER:
Timer interrupt enable register
TSR:
Timer status register
TGR (A, B, C, D): Timer general registers (A, B, C, D)
TCNT:
Timer counter
Interrupt request signals
Channel 3:
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4:
TGI4A
TGI4B
TCI4V
TCI4U
Channel 5:
TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
A/D conversion start request signal
PPG output trigger signal
Interrupt request signals
Channel 0:
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1:
TGI1A
TGI1B
TCI1V
TCI1U
Channel 2:
TGI2A
TGI2B
TCI2V
TCI2U

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