Figure 15.4 Example Of A/D Conversion (Scan Mode, Three Channels (An0 To An2) Selected) - Renesas H8SX/1520 Series Hardware Manual

Section 15 A/D Converter
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
ADST
ADF
Channel 0 (AN0)
operation state
Channel 1 (AN1)
operation state
Channel 2 (AN2)
operation state
Channel 3 (AN3)
operation state
ADDRA
ADDRB
ADDRC
ADDRD
↓ indicates the timing of instruction execution by software.
Notes: 1.
2. Data being converted is ignored.
Rev. 3.00 Mar. 14, 2006 Page 558 of 804
REJ09B0104-0300
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A/D conversion consecutive execution
Set *
1
A/D
Waiting for
conver-
conversion
sion 1
Waiting for conversion
Waiting for conversion
Waiting for conversion
Transfer
Figure 15.4 Example of A/D Conversion
(Scan Mode, Three Channels (AN0 to AN2) Selected)
A/D conversion time
Waiting for conversion
A/D
conver-
Waiting for conversion
sion 2
A/D
conver-
sion 3
A/D conversion result 1
Clear *
A/D Waiting for conversion
conver-
sion 4
A/D
Waiting for
2
conver-
*
conversion
sion 5
Waiting for conversion
A/D conversion result 4
A/D conversion result 2
A/D conversion result 3
1
Clear *
1