Table 9.12 TPSC2 to TPSC0 (Channel 4)
Bit 2
Channel
TPSC2
4
0
0
0
0
1
1
1
1
Note: This setting is ignored when channel 4 is in phase counting mode.
Table 9.13 TPSC2 to TPSC0 (Channel 5)
Bit 2
Channel
TPSC2
5
0
0
0
0
1
1
1
1
Note: This setting is ignored when channel 5 is in phase counting mode.
Bit 1
Bit 0
TPSC1
TPSC0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Bit 1
Bit 0
TPSC1
TPSC0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Section 9 16-Bit Timer Pulse Unit (TPU)
Description
Internal clock: counts on Pφ/1
Internal clock: counts on Pφ/4
Internal clock: counts on Pφ/16
Internal clock: counts on Pφ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKC pin input
Internal clock: counts on Pφ/1024
Counts on TCNT5 overflow/underflow
Description
Internal clock: counts on Pφ/1
Internal clock: counts on Pφ/4
Internal clock: counts on Pφ/16
Internal clock: counts on Pφ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKC pin input
Internal clock: counts on Pφ/256
External clock: counts on TCLKD pin input
Rev. 3.00 Mar. 14, 2006 Page 269 of 804
REJ09B0104-0300