Mailbox Interrupt Mask Register (Mbimr) - Renesas H8SX/1520 Series Hardware Manual

Section 13 Controller Area Network (HCAN)

13.3.12 Mailbox Interrupt Mask Register (MBIMR)

MBIMR enables or disables interrupt requests by individual mailboxes.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
15 MBIMR7
14 MBIMR6
13 MBIMR5
12 MBIMR4
11 MBIMR3
10 MBIMR2
9 MBIMR1
8 MBIMR0
7 MBIMR15
6 MBIMR14
5 MBIMR13
4 MBIMR12
3 MBIMR11
2 MBIMR10
1 MBIMR9
0 MBIMR8
Rev. 3.00 Mar. 14, 2006 Page 470 of 804
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15 14
MBIMR7 MBIMR6 MBIMR5
1 1
R/W R/W
7 6
MBIMR15 MBIMR14 MBIMR13
1 1
R/W R/W
Initial
Value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
13 12 11
MBIMR4 MBIMR3
1 1 1
R/W R/W R/W
5 4 3
MBIMR12 MBIMR11
1 1 1
R/W R/W R/W
R/W Description
R/W
Mailbox Interrupt Mask (MBIMRx)
R/W When MBIMRn (n = 1 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When
R/W
set to 1, the interrupt request is masked.
R/W
The interrupt source in a transmit mailbox is TXPR
R/W
clearing caused by transmission end or
transmission cancellation. The interrupt source in
R/W
a receive mailbox is RXPR setting on reception
R/W
end.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
10 9
MBIMR2 MBIMR1 MBIMR0
1 1
R/W R/W
2 1
MBIMR10 MBIMR9 MBIMR8
1 1
R/W R/W
8
1
R/W
0
1
R/W