Usage Notes; Conflict Between Interrupt Generation And Disabling; Figure 5.7 Conflict Between Interrupt Generation And Disabling - Renesas H8SX/1520 Series Hardware Manual

Section 5 Interrupt Controller
5.8

Usage Notes

5.8.1

Conflict between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request with priority
over that interrupt, interrupt exception handling will be executed for the interrupt with priority,
and another interrupt will be ignored. The same also applies when an interrupt source flag is
cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared
to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
φ
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Rev. 3.00 Mar. 14, 2006 Page 122 of 804
REJ09B0104-0300
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TIER_0 write cycle by CPU
TIER_0 address

Figure 5.7 Conflict between Interrupt Generation and Disabling

TCIV exception handling