Figure 7.38 Interrupt And Interrupt Sources; Figure 7.39 Procedure Example Of Resuming Transfer By Clearing Interrupt Source - Renesas H8SX/1500 Series Hardware Manual

Section 7 DMA Controller (DMAC)
TSIE bit
DMAC is activated in
transfer size error state
RPTIE bit
DMAC is activated
after BKSZ bits are
changed from 1 to 0
SARIE bit
Extended repeat area
overflow occurs in
source address
DARIE bit
Extended repeat area
overflow occurs in
destination address
Transfer end interrupt
handling routine
Consecutive transfer
Registers are specified
DTE bit is set to 1
Interrupt handling routine
ends (RTE instruction
Transfer resume
processing end
[1] Specify the values in the registers such as transfer counter and address register.
[2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or
ESIF bit in DMDR to 0 and an interrupt source is cleared.
[3] End the interrupt handling routine by the RTE instruction.
[4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit.
[5] Complete the interrupt handling routine and clear the interrupt mask.
[6] Specify the values in the registers such as transfer counter and address register.
[7] Set the DTE bit to 1 to resume DMA operation.

Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source

Rev. 3.00 Mar. 14, 2006 Page 202 of 804
REJ09B0104-0300

Figure 7.38 Interrupt and Interrupt Sources

processing
[1]
[2]
[3]
executed)
DTIE bit
DTIF bit
[Setting condition]
When DTCR becomes 0
and transfer ends
ESIE bit
ESIF bit
Setting condition is satisfied
Transfer resumed after
interrupt handling routine
DTIF and ESIF bits are
cleared to 0
Interrupt handling routine
ends
Registers are specified
DTE bit is set to 1
Transfer resume
processing end
Transfer end
interrupt
Transfer escape
end interrupt
[4]
[5]
[6]
[7]