Ssu Mode; Figure 14.4 Example Of Initial Settings In Ssu Mode - Renesas H8SX/1520 Series Hardware Manual

Section 14 Synchronous Serial Communication Unit (SSU)
14.4.5

SSU Mode

In SSU mode, data communications are performed via four lines: clock line (SSCK), data input
line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS).
In addition, the SSU supports bidirectional mode in which a single pin functions as data input and
data output lines.
(1)
Initial Settings in SSU Mode
Figure 14.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both
the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1]
Specify MSS, BIDE, SOL, SCKS, CSS1,
[2]
and CSS0 bits in SSCRH
Clear SSUMS in SSCRH to 0 and
[3]
specify bits DATS1 and DATS0
Specify MLS, CPOS, CPHS, CKS2,
[4]
CKS1, and CKS0 bits in SSMR
Specify SDOS, SSCKOS, SCSOS,
TENDSTS, SCSATS and SSODTS
Specify TE, RE, TEIE, TIE, RIE,
[5]
and CEIE bits in SSER simultaneously
Rev. 3.00 Mar. 14, 2006 Page 530 of 804
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Set a bit in ICR to 1
bits in SSCR2
End

Figure 14.4 Example of Initial Settings in SSU Mode

[1] When the pin is used as an input.
[2] Specify master/slave mode selection, bidirectional mode enable,
SSO pin output value selection, SSCK pin selection, and SCS pin
selection.
[3] Selects SSU mode and specify transmit/receive data length.
[4] Specify MSB first/LSB first selection, clock polarity selection,
clock phase selection, and transfer clock rate selection.
[5] Enables/disables interrupt request to the CPU.