Interrupt Sources; Table 7.6 Interrupt Sources And Priority - Renesas H8SX/1500 Series Hardware Manual

Section 7 DMA Controller (DMAC)
7.7

Interrupt Sources

The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer
escape end interrupt which is generated when a transfer is terminated before the transfer counter
reaches 0. Table 7.6 shows interrupt sources and priority.
Table 7.6 Interrupt Sources and Priority
Abbr. Interrupt Sources
DMTEND0 Transfer end interrupt by channel 0 transfer counter
DMTEND1 Transfer end interrupt by channel 1 transfer counter
DMTEND2 Transfer end interrupt by channel 2 transfer counter
DMTEND3 Transfer end interrupt by channel 3 transfer counter
DMEEND0
Interrupt by channel 0 transfer size error
Interrupt by channel 0 repeat size end
Interrupt by channel 0 extended repeat area overflow on source address
Interrupt by channel 0 extended repeat area overflow on destination address
DMEEND1
Interrupt by channel 1 transfer size error
Interrupt by channel 1 repeat size end
Interrupt by channel 1 extended repeat area overflow on source address
Interrupt by channel 1 extended repeat area overflow on destination address
DMEEND2
Interrupt by channel 2 transfer size error
Interrupt by channel 2 repeat size end
Interrupt by channel 2 extended repeat area overflow on source address
Interrupt by channel 2 extended repeat area overflow on destination address
DMEEND3
Interrupt by channel 3 transfer size error
Interrupt by channel 3 repeat size end
Interrupt by channel 3 extended repeat area overflow on source address
Interrupt by channel 3 extended repeat area overflow on destination address
Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding
channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in
DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in
DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels are
decided by the interrupt controller and it is shown in table 7.6. For details, see section 5, Interrupt
Controller.
Rev. 3.00 Mar. 14, 2006 Page 200 of 804
REJ09B0104-0300
Priority
High
Low