Transmit Wait Register (Txpr) - Renesas H8SX/1500 Series Hardware Manual

13.3.5

Transmit Wait Register (TXPR)

TXPR makes transmit messages stored in mailboxes enter the transmit wait state (CAN bus
arbitration wait).
Bit 15
Bit Name TXPR7
Initial Value 0
R/W R/W
Bit 7
Bit Name TXPR15
Initial Value 0
R/W R/W
Bit Bit Name
15 TXPR7
14 TXPR6
13 TXPR5
12 TXPR4
11 TXPR3
10 TXPR2
9 TXPR1

8
7 TXPR15
6 TXPR14
5 TXPR13
4 TXPR12
3 TXPR11
2 TXPR10
1 TXPR9
0 TXPR8
14 13
TXPR6 TXPR5 TXPR4
0 0
R/W R/W
6 5
TXPR14 TXPR13 TXPR12
0 0
R/W R/W
Initial
Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Section 13 Controller Area Network (HCAN)
12 11 10
TXPR3 TXPR2
0 0
R/W R/W R/W
4 3
TXPR11 TXPR10
0 0
R/W R/W R/W
Description
These bits set a transmit wait (CAN bus arbitration
wait) for the corresponding mailboxes 1 to 15.
When TXPRn (n = 1 to 15) is set to 1, the
message in mailbox n becomes the transmit wait
state.
[Clearing conditions]
Completion of message transmission
Completion of transmission cancellation
Bit 8 is reserved. This is a read-only bit and cannot
be modified.
Rev. 3.00 Mar. 14, 2006 Page 459 of 804
9 8
TXPR1 —
0 0 1
R
R/W
2 1 0
TXPR9 TXPR8
0 0 0
R/W R/W
REJ09B0104-0300