Figure 7.1 Block Diagram Of Dmac - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer

Hide thumbs Also See for H8SX/1500 Series:

Table of Contents

A block diagram of the DMAC is shown in figure 7.1.

Interrupt signals

requested to the

Internal activation sources

Internal activation

source detector

DSAR_n: DMA source address register

DDAR_n: DMA destination address register DACKn: DMA transfer acknowledge

DOFR_n: DMA offset register

DTCR_n: DMA transfer count register

DBSR_n: DMA block size register

DMDR_n: DMA mode control register

DACR_n: DMA address control register

Note: * Auto request activation and single address mode are not supported by the

External pins

Module data bus

H8SX/1520 Group.

Figure 7.1 Block Diagram of DMAC

Internal address bus

Address buffer

Operation unit

DREQn: DMA transfer request

TENDn: DMA transfer end

DMA module request select register

Rev. 3.00 Mar. 14, 2006 Page 135 of 804

Section 7 DMA Controller (DMAC)

Internal data bus

REJ09B0104-0300

Table of Contents