Table 9.1 Unit Configuration For Each Product; Table 9.2 Tpu Functions (Unit 0) - Renesas H8SX/1500 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
Note: * The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for
channels 4 and 5. Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at
an input capture input and a compare match cannot be output.
Table 9.1 Unit Configuration for Each Product
Product
H8SX/1527
H8SX/1525
Note: * The H8SX/1525 does not include unit 0.
Table 9.2 TPU Functions (Unit 0)
Item
Count clock
General registers (TGR)
General registers/
buffer registers
I/O pins
Counter clear function
Compare 0 output
match
1 output
output
Toggle
output
Input capture function
Synchronous operation
Rev. 3.00 Mar. 14, 2006 Page 252 of 804
REJ09B0104-0300
Unit Configuration
Unit 0
Unit 1
Unit 1
Channel 0 Channel 1
Pφ/1 Pφ/1
Pφ/4 Pφ/4
Pφ/16 Pφ/16
Pφ/64 Pφ/64
TCLKA Pφ/256
TCLKB TCLKA
TCLKC TCLKB
TCLKD
TGRA_0 TGRA_1
TGRB_0 TGRB_1

TGRC_0
TGRD_0
TIOCA0 TIOCA1
TIOCB0 TIOCB1
TIOCC0
TIOCD0
TGR TGR
compare compare
match or match or
input input
capture capture
O O
O O
O O
O O
O O
Channel Configuration
Channels 0 to 5
Channels 6 to 11
Channels 6 to 11
Channel 2 Channel 3
Pφ/1 Pφ/1
Pφ/4 Pφ/4
Pφ/16 Pφ/16
Pφ/64 Pφ/64
Pφ/1024 Pφ/256
TCLKA Pφ/1024
TCLKB Pφ/4096
TCLKC TCLKA
TGRA_2 TGRA_3
TGRB_2 TGRB_3

TGRC_3
TGRD_3
TIOCA2 TIOCA3
TIOCB2 TIOCB3
TIOCC3
TIOCD3
TGR TGR
compare compare
match or match or
input input
capture capture
O O
O O
O O
O O
O O
Channel 4 Channel 5
Pφ/1 Pφ/1
Pφ/4 Pφ/4
Pφ/16 Pφ/16
Pφ/64 Pφ/64
Pφ/1024 Pφ/256
TCLKA TCLKA
TCLKC TCLKC
TCLKD
TGRA_4 TGRA_5
TGRB_4 TGRB_5
 
1 1
TIOCA4* TIOCA5*
1 1
TIOCB4* TIOCB5*
TGR TGR
compare compare
match or match or
input input
2 2
capture* capture*
1 1
O* O*
1 1
O* O*
1 1
O* O*
2 2
O* O*
O O