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Table 17.3 Registers/Parameters and Target Modes
Register/Parameter
Programming/
erasing interface
registers
Programming/
erasing interface
parameters
RAM emulation
Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target memory MAT.
17.7.1
Programming/Erasing Interface Registers
The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes.
These registers are initialized by a power-on reset.
(1)
Flash Code Control/Status Register (FCCS)
FCCS monitors errors during programming/erasing the flash memory and requests the on-chip
program to be downloaded to the on-chip RAM.
Bit
Bit Name
Initial Value
R/W
Downloaded from
Elcodis.com
electronic components distributor
Down-
load
FCCS
O
FPCS
O
FECS
O
FKEY
O
FMATS
FTDAR
O
DPFR
O
FPFR
FPEFEQ
FMPAR
FMPDR
FEBS
RAMER
7
6
5
—
—
—
1
0
0
R
R
R
Section 17 Flash Memory (0.18-(m F-ZTAT Version)
Initiali-
Program-
zation
ming
O
1
O*
O
O
O
O
O
4
3
FLER
—
0
0
R
R
Rev. 3.00 Mar. 14, 2006 Page 579 of 804
Erasure
Read
O
1
2
O*
O*
O
O
2
1
—
—
0
0
R
R
REJ09B0104-0300
RAM
Emulation
O
0
SCO
0
(R)/W
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