Smi, Hirq1, Hirq3, Hirq4, Hirq5, Hirq6, Hirq7, Hirq8, Hirq9; Hirq10, Hirq11, Hirq12, Hirq13, Hirq14, And Hirq15 - Renesas H8S/2100 Series Hardware Manual

20.5.2

SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9,

HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15

The LPC interface can request 15 kinds of host interrupt by means of SERIRQ. HIRQ1 and
HIRQ12 are used on LPC channel 1 and the SCIF, while SMI, HIRQ6, HIRQ9, HIRQ10, and
HIRQ11 can be requested from LPC channel 2, 3, 4 or SCIF. HIRQ3, HIRQ4, HIRQ5, HIRQ7,
HIRQ8, HIRQ13, HIRQ14, and HIRQ15 are only for the SCIF.
There are two ways of clearing a host interrupt request when the LPC channels are used.
When the IEDIR bit in SIRQCR is cleared to 0, host interrupt sources and LPC channels are all
linked to the host interrupt request enable bits. When the OBF flag is cleared to 0 by a read of
ODR or TWR15 by the host in the corresponding LPC channel, the corresponding host interrupt
enable bit is automatically cleared to 0, and the host interrupt request is cleared.
When the IEDIR bit is set to 1 in SIRQCR, a host interrupt is requested by the only upon the host
interrupt enable bits. The host interrupt enable bit is not cleared when OBF is cleared. Therefore,
SMIE1, SMIE2, SMIE3A and SMIE3B, SMIE4, IRQ6En, IRQ9En, IRQ10En, and IRQ11En lose
their respective functional differences. In order to clear a host interrupt request, it is necessary to
clear the host interrupt enable bit. (n = 2 to 4.)
When the SCIF channels are used, clearing the DDCD bit in FMSR of the SCIF clears a host
interrupt request.
Table 20.10 summarizes the methods of setting and clearing these bits when the LPC channels are
used, and table 20.11 summarizes the methods of setting and clearing these bits when the SCIF
channels are used. Figure 20.8 shows the processing flowchart.
Section 20 LPC Interface (LPC)
Rev. 1.00 Apr. 28, 2008 Page 675 of 994
REJ09B0452-0100