Figure 10.1 Block Diagram Of Tpu - Renesas H8S Series Hardware Manual

Section 10 16-Bit Timer Pulse Unit (TPU)
Input/output pins
Channel 3:
TIOCA3
TIOCB3
TIOCC3
TIOCD3
Channel 4:
TIOCA4
TIOCB4
Channel 5:
TIOCA5
TIOCB5
Clock input
φ/1
Internal clock:
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
External clock:
TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
Channel 0:
TIOCA0
TIOCB0
TIOCC0
TIOCD0
Channel 1:
TIOCA1
TIOCB1
Channel 2:
TIOCA2
TIOCB2
Legend:
TSTR: Timer start register
TSYR: Timer synchro register
TCR: Timer control register
TMDR: Timer mode register
Rev. 6.00 Mar 15, 2006 page 162 of 570
REJ09B0211-0600
Timer I/O control registers (H, L)
TIOR (H, L):
Timer interrupt enable register
TIER:
Timer status register
TSR:
TImer general registers (A to D)
TGR (A to D):

Figure 10.1 Block Diagram of TPU

Interrupt request signals
Channel 3: TGIA_3
TGIB_3
TGIC_3
TGID_3
TCIV_3
Channel 4: TGIA_4
TGIB_4
TCIV_4
TCIU_4
Channel 5: TGIA_5
TGIB_5
TCIV_5
TCIU_5
Internal data bus
A/D converter convertion start signal
PPG output trigger signal
Interrupt request signals
Channel 3: TGIA_0
TGIB_0
TGIC_0
TGID_0
TCIV_0
Channel 4: TGIA_1
TGIB_1
TCIV_1
TCIU_1
Channel 5: TGIA_2
TGIB_2
TCIV_2
TCIU_2