Motorola MPC860 PowerQUICC User Manual page 6

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4.1 PowerPC Architecture Overview .........................................................................4-1
4.1.1 Levels of the PowerPC Architecture ................................................................4-3
4.2 Features.................................................................................................................4-4
4.3 Basic Structure of the Core...................................................................................4-5
4.3.1 Instruction Flow................................................................................................4-6
4.3.2 Basic Instruction Pipeline.................................................................................4-7
4.3.3 Instruction Unit.................................................................................................4-7
4.3.3.1 Branch Operations ........................................................................................4-7
4.3.3.2 Dispatching Instructions...............................................................................4-9
4.4 Register Set...........................................................................................................4-9
4.5 Execution Units ....................................................................................................4-9
4.5.1 Branch Processing Unit ..................................................................................4-10
4.5.2 Integer Unit.....................................................................................................4-10
4.5.3 Load/Store Unit ..............................................................................................4-10
4.5.3.1 Executing Load/Store Instructions .............................................................4-12
4.5.3.2 Serializing Load/Store Instructions ............................................................4-12
4.5.3.3 Store Accesses ............................................................................................4-12
4.5.3.4 Nonspeculative Load Instructions ..............................................................4-12
4.5.3.5 Unaligned Accesses....................................................................................4-13
4.5.3.6 Atomic Update Primitives ..........................................................................4-13
4.6 The MPC860 and the PowerPC Architecture.....................................................4-14
5.1 MPC860 Register Implementation .......................................................................5-1
5.1.1 PowerPC RegistersÑUser Registers................................................................5-2
5.1.1.1 PowerPC User-Level Register Bit Assignments ..........................................5-2
5.1.1.1.1
5.1.1.1.2
5.1.1.1.3
5.1.1.1.4
5.1.2 PowerPC RegistersÑSupervisor Registers......................................................5-4
5.1.2.1 DAR, DSISR, and BAR Operation ..............................................................5-5
5.1.2.2 Unsupported Registers .................................................................................5-6
5.1.2.3 PowerPC Supervisor-Level Register Bit Assignments ................................5-6
5.1.2.3.1
5.1.2.3.2
5.1.3 MPC860-Specific SPRs....................................................................................5-8
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CONTENTS
Chapter 4
The PowerPC Core
Chapter 5
PowerPC Core Register Set
Condition Register (CR)...........................................................................5-2
Condition Register CR0 Field Definition.................................................5-3
XER ..........................................................................................................5-3
Time Base Registers.................................................................................5-4
Machine State Register (MSR) ................................................................5-6
Processor Version Register ......................................................................5-8
MPC860 PowerQUICC UserÕs Manual
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