Motorola PowerQUICC II MPC8280 Series Reference Manual page 446

Basic Architecture
the logical value of the external signals specified in the RAM array is output on the
corresponding UPM pins.
Figure 11-4 shows a basic configuration.
Address (A),
Address
Type (AT)
Address
Comparator
Bank Select
MS/BS
Fields
Figure 11-4. Basic Memory Controller Operation
The SDRAM mode registers (LSDMR and PSDMR) define the global parameters for the
60x and local SDRAM devices. Machine A/B/C mode registers (MxMR) define most of the
global features for each UPM. GPCM parameters are defined in the option register (ORx).
Some SDRAM and UPM parameters are also defined in ORx.
11.2.1 Address and Address Space Checking
The defined base address is written to the BRx. The bank size is written to the ORx. Each
time a bus cycle access is requested on the 60x or local bus, addresses are compared with
each bank. If a match is found on a memory controller bank, the attributes defined in the
BRx and ORx for that bank are used to control the memory access. If a match is found in
more than one bank, the lowest-numbered bank handles the memory access (that is, bank 0
has priority over bank 1).
Although 60x bus accesses that hit a bank allocated to the local
bus are transferred to the local bus, local bus access hits to
banks allocated to the 60x bus are ignored. 60x-to-local bus
transactions have priority over regular memory bank hits.
11-8
Freescale Semiconductor, Inc.
Internal/External Memory Access Request Select
SDRAM Machine
NOTE
MPC8280 PowerQUICC II Family Reference Manual
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UPMx GPCM
Signals
Timing
Generator
MUX
External Signals
MOTOROLA