Motorola PowerQUICC II MPC8280 Series Reference Manual page 450

Basic Architecture
11.2.11 External Address Latch Enable Signal (ALE)
The memory controller provides control for an external address latch, needed on the 60x
bus in 60x compatible mode. ALE is asserted for one clock cycle on the first cycle of each
memory-controller transaction. In this section, whenever ALE is not on a timing diagram,
assume that it is asserted on the first cycle in which CS can be asserted.
ALE is relevant only on the 60x bus and only in
60x-compatible mode.
11.2.12 ECC/Parity Byte Select (PBSE)
Systems that use ECC or read-modify-write parity, require an additional memory device
that requires byte-select like a normal data device. ANDing BS[0–7] through external logic
to achieve the logical function of this byte-select can affect the memory access timing
because it adds a delay to the byte-select path. The MPC8280's memory controller provides
optional byte-select pins that are an internal AND of the eight byte selects, allowing
glueless, faster connection to ECC/RMW-parity devices.
This option is enabled by setting SIUMCR[PBSE], as described in Section 4.3.2.6, "SIU
Module Configuration Register (SIUMCR)."
11.2.13 Partial Data Valid Indication (PSDVAL)
The 60x and local buses have an internal 64-bit data bus. According to the 60x bus
specification, TA is asserted when up to a double word of data is transferred. Because the
MPC8280 supports memories with port sizes smaller than 64 bits, there is a need for partial
data valid indication. The memory controller uses PSDVAL to indicate that data is latched
by the memory on write accesses or valid data is present on read accesses. The quantity of
the data depends on the memory port size and the transfer size. The memory controller
accumulates PSDVAL assertions, and when a double word (or the transfer size) is
transferred, the memory controller asserts TA to indicate that a 60x data beat was
transferred. Table 11-1 shows the number of PSDVAL assertions needed for one TA
assertion under various circumstances.
Table 11-1. Number of PSDVAL Assertions Needed for TA Assertion
Port Size
64
32
32 Word/half word/byte (32-bit aligned)
16
16
11-12
Freescale Semiconductor, Inc.
NOTE
Transfer Size
Any
Double word
Double Word
Word
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
PSDVAL Assertions
1
2
1
4
2
TA Assertions
1
1
1
1
1
MOTOROLA