Signal Description - Samsung S3C2501X User Manual

PRODUCT OVERVIEW

1.6 SIGNAL DESCRIPTION

Group Pin Name
System XCLK
Config
(20)
HCLKO
CLKSEL
BUS_FILTER
PHY_FREQ
PHY_CLKSEL
PHY_FILTER
PHY_CLKO
CPU_FILTER
1-12
Table 1-1. S3C2501X Signal Descriptions
Pin Type Pad Type
1 I Phic
1 O phbst24
1 I Phic
1 I poar50_abb
1 I Phic
1 I Phic
1 O poar50_abb
1 O phob8
1 O poar50_abb
Description
S3C2501X PLL Clock Source. If CLKSEL is
Low, PLL output clock is used as the system
clock. If CLKSEL is high, XCLK is used as the
system clock.
System clock output. The internal system
clock is monitored via HCLKO. If SDRAM is
used, this clock should be used SDRAM clock.
Clock Select for CPU PLL and system PLL.
If CLKSEL is low, CPU PLL clock is used as
ARM940T source clock and system PLL clock
is used system clock source, depending on
CLKMOD[1:0]. If CLKSEL is high, XCLK is
used both clock sources.
PLL filter pin for System PLL.
If the PLL is used, 320pF capacitor should be
connected between the pin and ground.
PHY clock frequency select for PHY PLL.
0 = 20MHz, 1 = 25MHz
Clock Select for PHY PLL
If this pin is set to low, the PHY PLL generates
clock depending on PHY_FREQ state. The
PHY PLL goes into power down mode with
PHY_CLKSEL set to high.
PLL filter pin for PHY PLL.
If the PLL is used, 320pF capacitor should be
connected between the pin and ground.
PHY clock Out
PHY PLL clock output can be monitored by
PHY_CLKO. This clock is used as the external
phy source clock.
PLL filter pin for System PLL.
If the PLL is used, 320pF capacitor should be
connected between the pin and ground.
S3C2501X