Μdma Channel Control Structure - Texas Instruments CC3200 Technical Reference Manual

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Offset
0x500
0x510
0x514
0x518
0x51C
0xFB0
4.3.2 µDMA Channel Control Structure
The μDMA channel control structure holds the transfer settings for a μDMA channel. Each channel has
two control structures, which are located in a table in system memory. The channel control structure is one
entry in the channel control table. Each channel has a primary and alternate structure. The primary control
structures are located at offsets 0x0, 0x10, 0x20 and so on. The alternate control structures are located at
offsets 0x200, 0x210, 0x220, and so on.
SWRU367D – June 2014 – Revised May 2018
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Table 4-4. µDMA Register Map (continued)
Name
DMA_CHASGN
DMA_CHMAP0
DMA_CHMAP1
DMA_CHMAP2
DMA_CHMAP3
DMA_PV
Copyright © 2014–2018, Texas Instruments Incorporated
Type Reset
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
R/W 0x0000.0000
RO 0x0000.0200
Direct Memory Access (DMA)
Register Description
Description
DMA Channel
Assignment
DMA Channel Map
Select 0
DMA Channel Map
Select 1
DMA Channel Map
Select 2
DMA Channel Map
Select 3
DMA peripheral Version
109