Dma - Texas Instruments MSPM0G350 Series Manual

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• LFOSC: Internal low-frequency oscillator (32 kHz)
• SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim, 16 MHz or 24 MHz with user
trim)
• LFXT/LFCKIN : Low-frequency external crystal oscillator or digital clock input (32 kHz)
• HFXT/HFCKIN: High-frequency external crystal oscillator or digital clock input (4 to 48 MHz)
• SYSPLL: System phase locked loop with 3 outputs (32 to 80 MHz)
The following clocks are distributed by the clock module for use by the processor, bus, and peripherals:
• MCLK: Main system clock for PD1 peripherals, derived from SYSOSC, LFCLK, or HSCLK, active in RUN and
SLEEP modes
• CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode
• ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes
• MFCLK: 4-MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modes
• MFPCLK: 4-MHz fixed mid-frequency precision clock, available in RUN, SLEEP, and STOP modes
• LFCLK: 32-kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and
STANDBY modes
• ADCCLK: ADC clock, available in RUN, SLEEP and STOP modes
• CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modes
• HFCLK: High-frequency clock derived from HFXT or HFCLK_IN, available in RUN and SLEEP mode
• HSCLK: High-speed clock derived from HFCLK or the SYSPLL, available in RUN and SLEEP mode
• CANCLK: CAN functional clock, derived from HFCLK or SYSPLL
For more details, see the CKM chapter of the
Manual.

8.5 DMA

The direct memory access (DMA) controller allows movement of data from one memory address to another
without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory
to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode,
without having to awaken to move data to or from a peripheral.
The DMA in these devices support the following key features:
• 7 independent DMA transfer channels
– 3 full-feature channel (DMA0, DMA1 and DMA2), supporting repeated transfer modes
– 4 basic channels (DMA3, DMA4, DMA5 and DMA6) supporting single transfer modes
• Configurable DMA channel priorities
• Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer
capability
• Transfer counter block size supports up to 64k transfers of any data type
• Configurable DMA transfer trigger selection
• Active channel interruption to service other channels
• Early interrupt generation for ping-pong buffer architecture
• Cascading channels upon completion of activity on another channel
• Stride mode to support data re-organization, such as 3-phase metering applications
Table 8-2 lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control
bits in the DMA memory mapped registers.
Trigger 0:12
0
1
2
3
4
Copyright © 2023 Texas Instruments Incorporated
MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Table 8-2. DMA Trigger Mapping
Source
Software
Generic Subscriber 0 (FSUB_0)
Generic Subscriber 1 (FSUB_1)
AES Publisher 1
AES Publisher 2
Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
Trigger 13:24
13
14
15
16
17
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SLASF88 – OCTOBER 2023
Source
SPI1 Publisher 1
SPI1 Publisher 2
UART3 Publisher 1
UART3 Publisher 2
UART0 Publisher 1
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