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Instruction
SUBV
Rm,Rn
Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required
when the operation result is read from the MAC register immediately after the
instruction.
2. The normal minimum number of execution cycles is one, but three cycles are required
when the operation result is read from the MAC register immediately after the MUL
instruction.
Logic Operation Instructions
Table 2.21 Logic Operation Instructions
Instruction
AND
Rm,Rn
AND
#imm,R0
AND.B
#imm,@(R0,GBR)
NOT
Rm,Rn
OR
Rm,Rn
OR
#imm,R0
OR.B
#imm,@(R0,GBR)
TAS.B
@Rn
TST
Rm,Rn
TST
#imm,R0
TST.B
#imm,@(R0,GBR)
XOR
Rm,Rn
XOR
#imm,R0
XOR.B
#imm,@(R0,GBR)
Instruction Code
0011nnnnmmmm1011
Instruction Code
0010nnnnmmmm1001
11001001iiiiiiii
11001101iiiiiiii
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
0100nnnn00011011
0010nnnnmmmm1000
11001000iiiiiiii
11001100iiiiiiii
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
Operation
Rn–Rm → Rn, Underflow → T 1
Operation
Rn & Rm → Rn
R0 & imm → R0
(R0 + GBR) & imm →
(R0 + GBR)
~Rm → Rn
Rn | Rm → Rn
R0 | imm → R0
(R0 + GBR) | imm →
(R0 + GBR)
If (Rn) is 0, 1 → T;
1 → MSB of (Rn)
Rn & Rm; if the result
is 0, 1 → T
R0 & imm; if the result
is 0, 1 → T
(R0 + GBR) & imm;
if the result is 0, 1 → T
Rn ^ Rm → Rn
R0 ^ imm → R0
(R0 + GBR) ^ imm →
(R0 + GBR)
Rev. 4.00 Sep. 14, 2005 Page 75 of 982
Section 2 CPU
Execution
States
T Bit
Underflow
Execution
States
T Bit
1
—
1
—
3
—
1
—
1
—
1
—
3
—
4
Test
result
1
Test
result
1
Test
result
3
Test
result
1
—
1
—
3
—
REJ09B0023-0400
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