Figure 25.37 Synchronous Dram Auto-Refreshing Timing (Wtrp = 1 Cycle, Wtrc = 3 Cycles) - Renesas HD6417641 Hardware Manual

Tp
CKIO
t
AD1
A25 to A0
t
AD1
1
A12/A11*
t
CSD1
CSn
t
RWD1
RD/WR
t
RASD1
RASU/L
CASU/L
DQMxx
D31 to D0
BS
CKE
DACKn*
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
3. Pins D31 to D16 with weak keeper are retained as weak keepers.
Figure 25.37 Synchronous DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles)
Tpw Trr Trc
t
AD1
t
AD1
t t t
CSD1 CSD1 CSD1
t
RWD1
t t t
RASD1 RASD1 RASD1
t t
CASD1 CASD1
3
(Hi-Z)*
(High)
Section 25 Electrical Characteristics
Trc Trc
t
RWD1
Rev. 4.00 Sep. 14, 2005 Page 949 of 982
REJ09B0023-0400