Block Diagram; Figure 1.1 Block Diagram - Renesas HD6417641 Hardware Manual

1.2

Block Diagram

The block diagram of this LSI is shown in figure1.1.
X/Y
Memory
U Memory
CACHE
[Legend]
ADC:
AUD:
BSC:
CACHE:
CMT:
CPG/WDT:
CPU:
DMAC:
BSC
External Bus
Interface
A/D converter
Advanced user debugger
Bus state controller
Cache memory
Compare match timer
Clock Pulse generator/Watch dog Timer
Central processing unit
Direct memory access controller

Figure 1.1 Block Diagram

SH3
CPU
DSP
UBC
AUD
INTC
CPG/
WDT
DMAC
I/O port
DSP: Digital signal processor
H-UDI: User debugging interface
INTC: Interrupt controller
SCIF: Serial communication interface
UBC: User break controller
MTU: Multi-Function Timer Pulse unit
USB : USB function module
2
IIC2: I C bus interface
Rev. 4.00 Sep. 14, 2005 Page 7 of 982
Section 1 Overview
USB
CMT
MTU
SCIF
ADC
H-UDI
IIC2
REJ09B0023-0400