Figure 10.2 Interrupt Operation Flowchart - Renesas HD6417641 Hardware Manual

Yes
Set interrupt sourse in
INTEVT2
Save SR to SSR;
save PC to SPC
Set BL/RB
bits in SR to1
Branch to exception
handler
I3 to I0: Interrupt mask bits in status register (SR)

Figure 10.2 Interrupt Operation Flowchart

Program
execution state
Interrupt
generated?
Yes
SR.BL=0
No
or sleep mode?
Yes
No
NMI?
Level 15
interrupt?
Yes
Yes to
I3 I0 level
14or lower?
No
Yes
Section 10 Interrupt Controller (INTC)
No
No
No
Level 14
interrupt?
Yes
Level 1
interrupt?
to
I3 I0 level
Yes
13 or lower?
No
to
I3
level 0?
Yes
No
Rev. 4.00 Sep. 14, 2005 Page 239 of 982
No
I0
REJ09B0023-0400