C Bus Mode Register (Icmr) - Renesas HD6417641 Hardware Manual

2
Section 16 I C Bus Interface 2 (IIC2)
Bit Bit Name
4 SDAOP
3 SCLO

2
1 IICRST

0
2
16.3.3 I

C Bus Mode Register (ICMR)

ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the transfer bit count.
ICMR is initialized to H'38 by a power-on reset.
Bit Bit Name
7 MLS

6
Rev. 4.00 Sep. 14, 2005 Page 480 of 982
REJ09B0023-0400
Initial
Value R/W Description
1 R/W SDAO Write Protect
This bit controls change of output level of the SDA pin
by modifying the SDAO bit. To change the output level,
clear SDAO and SDAOP to 0 or set SDAO to 1 and
clear SDAOP to 0. This bit is always read as 1.
1 R This bit monitors SCL output level. When SCLO is 1,
SCL pin outputs high. When SCLO is 0, SCL pin
outputs low.

1 Reserved
This bit is always read as 1, and cannot be modified.
0 R/W IIC Control Part Reset
This bit resets the control part except for I
this bit is set to 1 when hang-up occurs because of
communication failure during I
part can be reset without setting ports and initializing
registers.

1 Reserved
This bit is always read as 1, and cannot be modified.
Initial
Value R/W Description
0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I

0 Reserved
The write value should always be 0.
2
C registers. If
2 2
C operation, I C control
2
C bus format is used.