Scan Mode - Renesas HD6417641 Hardware Manual

Section 21 A/D Converter
21.3.3

Scan Mode

Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit in the A/D control/status register (ADCSR0 or ADCSR1) is set to 1 by software, A/D
conversion starts on the first channel in the group (A/D0 when AN0, A/D1 when AN4). When two
or more channels are selected, after conversion of the first channel ends, conversion of the second
channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected
channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into
the A/D data registers corresponding to the channels.
When the mode or analog input channel must be changed during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the
necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in
the group. The ADST bit can be set at the same time as the mode or channel selection is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 21.4 shows a timing diagram for this example.
1. Scan modes are selected, analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0),
and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA0.
3. Next, conversion of the second channel (AN1) starts automatically.
4. Conversion proceeds in the same way through the third channel (AN2).
5. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI0
interrupt is requested at this time.
6. The ADST bit is not cleared automatically. Steps 2 to 4 are repeated as long as the ADST bit
remains set to 1. When steps 2 to 4 are repeated, the ADF flag is keep to 1. When the ADST
bit is cleared to 0, A/D conversion stops. The ADF bit cleared by reading ADF while ADF=1,
then writing 0 to ADF.
7. If the ADIE bit is set to 1 and the ADF flag is set to 1 in steps 2 to 4 are repeated, an ADI0
interrupt is requested ad all times. When an ADI0 interrupt is requested at conversion ends of
all the selected channels, the ADF bit is cleared to 0 after an ADI0 interrupt is requested.
Rev. 4.00 Sep. 14, 2005 Page 808 of 982
REJ09B0023-0400