Control Signal Timing; Table 25.7 Control Signal Timing - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
25.3.2

Control Signal Timing

Table 25.7 Control Signal Timing

Q = 3.0 V to 3.6 V, V
Conditions: V
CC
= 0 V, Ta = −40°C to +85°C
AV
SS
Item
RESETP pulse width
RESETP setup time*
1
RESETP hold time
RESETM pulse width
RESETM setup time
RESETM hold time
BREQ setup time
BREQ hold time
NMI setup time*
1
NMI hold time
IRQ7 to IRQ0 setup time*
IRQ7 to IRQ0 hold time
BACK delay time
STATUS1, STATUS0 delay time
Bus tri-state delay time 1
Bus tri-state delay time 2
Bus buffer on time 1
Buss buffer on time 2
Notes: 1. The RESETP, NMI and IRQ7 to IRQ0 signals are asynchronous signals. When the
setup time is satisfied, change of signal level is detected at the rising edge of the clock.
If not, the detection is delayed until the rising edge of the clock.
2. In standby mode, t
(100 µs)
3. In standby mode, t
must be held low until signals STATUS0 and STATUS1 indicate the reset state (HH).
4. Bcyc indicates external clock cycle time. (B clock cycle)
Rev. 4.00 Sep. 14, 2005 Page 920 of 982
REJ09B0023-0400
= 1.8 V ±5%, AV
CC
Symbol
t
RESPW
t
RESPS
t
RESPH
t
RESMW
t
RESMS
t
RESMH
t
BREQS
t
BREQH
t
NMIS
t
NMIH
1
t
IRQS
t
IRQH
t
BACKD
t
STD
t
BOFF1
t
BOFF2
t
BON1
t
BON2
= t (10 ms). When multiplier of the clock is changed, t
RESP OSC2
(10 ms). When multiplier of the clock is changed, RESETM
= t
RESP OSC2
= 2.7 V to 3.6 V, V
CC
2
Bφ = 50 MHz*
Min. Max.
2
20* —
22 —
2 —
3
12* —
22 —
12 —
1/2t + 10 —
cyc
1/2t + 10 —
cyc
30 —
30 —
30 —
30 —
— 1/2t + 13 ns
cyc
— 100
0 100
0 100
0 30
0 30
Q = V =
SS SS
Unit Figure(s)
4
Bcyc* 25.5, 25.6, 25.9, and
25.10
ns
ns
4
Bcyc*
ns
ns
ns 25.11
ns
ns 25.10
ns
ns
ns
25.11, 25.12
ns
ns
ns
ns
ns
REPW
= t
PLL1