Renesas HD6417641 Hardware Manual page 362

Section 12 Bus State Controller (BSC)
Burst ROM (Clock Synchronous):
• CS0WCR
Bit Bit Name

31 to 18
17 BW1
16 BW0

15 to 11
Rev. 4.00 Sep. 14, 2005 Page 312 of 982
REJ09B0023-0400
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Number of Burst Wait Cycles
0 R/W Specify the number of wait cycles to be inserted
between the second or later access cycles in burst
access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.