Figure 13.2 Dma Transfer Flowchart - Renesas HD6417641 Hardware Manual

Figure 13.2 is a flowchart of this procedure.
Initial settings
(SAR, DAR, DMATCR, CHCR,
DMAOR, DMARS)
DE, DME = 1 and
NMIF, AE, TE = 0?
Transfer request
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR, SAR and
DAR updated
DMATCR = 0?
DEI interrupt request (when IE = 1)
or AE = 1 or DE = 0
Notes: 1. In auto-request mode, transfer begins when NMIF and TE are all 0 and the DE and DME bits are
set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
Start
No
Yes
No
1
occurs?*
Yes
No
Yes
TE = 1
NMIF = 1
No
or DME = 0?
Yes
Transfer end

Figure 13.2 DMA Transfer Flowchart

Section 13 Direct Memory Access Controller (DMAC)
3
*
transfer request mode,
DREQ detection selection
or AE = 1 or DE = 0
Normal end
Rev. 4.00 Sep. 14, 2005 Page 425 of 982
2
*
Bus mode,
system
NMIF = 1 No
or DME = 0?
Yes
Transfer aborted
REJ09B0023-0400