Figure 19.8 Sample Flowchart For Receiving Serial Data (Cont) - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
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Error handling
ORER = 1?
Yes
Overrun error handling
ER = 1?
Yes
Receive error handling
BRK = 1?
Yes
Break handling
DR = 1?
Yes
Read receive data in SCFRDR
Clear DR, ER, BRK flags
in SCFSR,
and ORER flag in SCLSR, to 0
End

Figure 19.8 Sample Flowchart for Receiving Serial Data (cont)

Section 19 Serial Communication Interface with FIFO (SCIF)
[1] Whether a framing error or parity error
No
has occurred in the receive data that
is to be read from SCFRDR can be
ascertained from the FER and PER
bits in SCFSR.
[2] When a break signal is received,
receive data is not transferred to
SCFRDR while the BRK flag is set.
However, note that the last data in
No
SCFRDR is H'00, and the break data
in which a framing error occurred is
stored.
No
No
Rev. 4.00 Sep. 14, 2005 Page 731 of 982
REJ09B0023-0400

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