Figure 20.9 Status Stage (Control-Out) Operation - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
Table of Contents

Advertisement

Status Stage (Control-OUT): The control-OUT status stage starts with an IN token from the
host. When an IN token is received at the start of the status stage, there is not yet any data in the
EP0iFIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from
this interrupt that the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is
written to the EP0i packet enable bit but no data is written to the EP0i FIFO. As a result, the next
IN token causes 0-byte data to be transmitted to the host, and control transfer ends.
After the application has finished all processing relating to the data stage, 1 should be written to
the EP0i packet enable bit.
IN token reception
in EP0i FIFO?
0-byte transmission to host
Set EP0i transmission
complete flag
(USBIFR0/EP0i TS = 1)
End of control transfer
USB function
No
Valid data
NACK
Yes
ACK
Interrupt request

Figure 20.9 Status Stage (Control-OUT) Operation

Clear EP0i transfer
Interrupt request
(USBIFR0/EP0i TR = 0)
Write 1 to EP0i packet
(USBTRG/EP0i PKTE = 1)
Clear EP0i transmission
(USBIFR0/EP0i TS = 0)
End of control transfer
Rev. 4.00 Sep. 14, 2005 Page 773 of 982
Section 20 USB Function Module
Application
request flag
enable bit
complete flag
REJ09B0023-0400

Advertisement

Table of Contents
loading

This manual is also suitable for:

Sh7641

Table of Contents