Cpu Instruction Formats; Table 2.13 Cpu Instruction Formats - Renesas HD6417641 Hardware Manual

Section 2 CPU
2.4.3

CPU Instruction Formats

Table 2.13 shows the instruction formats, and the meaning of the source and destination operands,
for instructions executed by the CPU core. The meaning of the operands depends on the
instruction code. The following symbols are used in the table.
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement

Table 2.13 CPU Instruction Formats

Instruction Format
0 type
15
xxxx xxxx xxxx
n type
15
xxxx nnnn xxxx
m type
15
xxxx
xxxx mmmm
Rev. 4.00 Sep. 14, 2005 Page 58 of 982
REJ09B0023-0400
Source
Operand

0
xxxx

0
xxxx
Control register or
system register
Control register or
system register
mmmm: register
direct
0
xxxx
mmmm: post-
increment register
indirect
mmmm: register
indirect
PC-relative using
Rm
Destination
Operand Sample Instruction

NOP
nnnn: register MOV T Rn
direct
nnnn: register STS
direct
nnnn: pre- STC.L
decrement register
indirect
Control register or LDC
system register
Control register or LDC.L
system register

JMP

BRAF
MACH,Rn
SR,@-Rn
Rm,SR
@Rm+,SR
@Rm
Rm