Port J Data Register (Pjdr); Table 23.12 Port J Data Register (Pjdr) Read/Write Operations - Renesas HD6417641 Hardware Manual

23.9.2

Port J Data Register (PJDR)

PJDR is a 13-bit readable/writable register with three reserved bits that stores data for pins PTJ12
to PTJ0. The PJDR is initialized to H'0000 by a power-on reset, but it retains its previous value by
a manual reset, in standby mode, or in sleep mode.
Bit Bit Name

15 to 13
12 PJ12DT
11 PJ11DT
10 PJ10DT
9 PJ9DT
8 PJ8DT
7 PJ7DT
6 PJ6DT
5 PJ5DT
4 PJ4DT
3 PJ3DT
2 PJ2DT
1 PJ1DT
0 PJ0DT

Table 23.12 Port J Data Register (PJDR) Read/Write Operations

PJnMD2 PJnMD1 Pin State
0 0
1
1 0
1
(n = 0 to 12)
Initial
Value R/W
All 0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Read
Input Pin state
Output PJDR value Data is written to PJDR and the value is

Reserved
Other functions Pin state
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Bits PJ12DT to PJ0DT correspond to pins PTJ12 to
PTJ0. When the pin function is general output port, the
value of the corresponding bit in PJDR is returned
directly by reading the port. When the function is
general input port, the corresponding pin level is read
by reading the port. Table 23.12 shows the function of
PJDR.
Write
Data is written to PJDR, but does not affect
pin state.
output from the pin.

Data is written to PJDR, but does not affect
pin state.
Rev. 4.00 Sep. 14, 2005 Page 863 of 982
Section 23 I/O Ports
REJ09B0023-0400