Shift Operations; Figure 3.9 Arithmetic Shift Operation Flow; Table 3.7 Variation Of Shift Operations - Renesas HD6417641 Hardware Manual

3.1.5

Shift Operations

Shift operations can use either register or immediate value as the shift amount operand. Other
source and destination operands are specified by the register. There are two kinds of shift
operations. Table 3.7 shows the variation of this type of operation. The correspondence between
each operand and registers, except for immediate operands, is the same as the ALU fixed-point
operations as shown in table 3.2.
Table 3.7 Variation of Shift Operations
Mnemonic Function
PSHA Sx, Sy, Dz Arithmetic shift
PSHL Sx, Sy, Dz Logical shift
PSHA #Imm1, Dz Arithmetic shift with
immediate.
PSHL #Imm2, Dz Logical shift with
immediate.
Note: –32 <= Imm1 <= +32, –16 <= Imm2 <= +16
Arithmetic Shift: Figure 3.9 shows the arithmetic shift operation flow.
7g 0g 31
Shift out
Shift amount data:
(Source 2)
Ignored
Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the
base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit
parts when a register not providing the guard-bit parts is specified as the source operand.
When a register not providing the guard-bit parts is specified as a destination operand, the
lower 32 bits of the operation result are input into the destination register.
Left Shift
16 15 0
> = 0
+32 to –32
7g 0g 31 23 22 16
Sy
6
Imm1

Figure 3.9 Arithmetic Shift Operation Flow

Source 1
Sx
Sx
Dz
Dz
7g 0g 31
0
(MSB copy)
< 0
15 0
0
Rev. 4.00 Sep. 14, 2005 Page 109 of 982
Section 3 DSP Operation
Source 2 Destination
Sy Dz
Sy Dz
Imm1 Dz
Imm2 Dz
Right Shift
16 15
GT Z N
Updated
DSR
REJ09B0023-0400
0
Shift out
V DC