Figure 16.10 Slave Transmit Mode Operation Timing (2) - Renesas HD6417641 Hardware Manual

SCL
9
(Master output)
SDA
A
(Master output)
SCL
(Slave output)
SDA
(Slave output)
TDRE
TEND
TRS
ICDRT
ICDRS
ICDRR
User
processing

Figure 16.10 Slave Transmit Mode Operation Timing (2)

1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Data n
[3] Clear TEND
Section 16 I
Slave transmit mode
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
[4] Read ICDRR (dummy read)
after clearing TRS
Rev. 4.00 Sep. 14, 2005 Page 495 of 982
2
C Bus Interface 2 (IIC2)
Slave receive
mode
9
A
[5] Clear TDRE
REJ09B0023-0400