Standby Mode; Table 6.3 Register States In Standby Mode - Renesas HD6417641 Hardware Manual

Section 6 Power-Down Modes
6.3.2

Standby Mode

1. Transition to Standby Mode
The LSI switches from a program execution state to a standby mode by executing the SLEEP
instruction when the STBY bit is 1 in STBCR register. In standby mode, not only the CPU but
also the clock and on-chip peripheral modules halt. The clock outputs from the CKIO and
CKIO2 pins also halt.
The contents of the CPU and cache registers remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. Table 6.3 lists the states of on-chip peripheral
modules registers in standby mode.
Table 6.3 Register States in Standby Mode
Module
Interrupt controller (INTC)
On-chip clock pulse generator (CPG) 
User break controller (UBC)
Bus state controller (BSC)
A/D converter (ADC)
I/O port
H-UDI
SCIF
USB
MTU
POE
DMAC
CMT
IIC2
The procedure for switching to standby mode is as follows:
A. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
B. Set the WDT's timer counter (WTCNT) to 0 and the CKS2 to CKS0 bits in the WTCSR
register to appropriate values to secure the specified oscillation settling time.
C. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed.
D. Standby mode is entered and the clocks within the chip are halted. The STATUS1 and
STATUS0 pins output low and high, respectively.
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