Break Address Mask Register B (Bamrb); Break Data Register B (Bdrb) - Renesas HD6417641 Hardware Manual

11.2.5

Break Address Mask Register B (BAMRB)

BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address
specified by BARB.
Bit Bit Name
31 to 0 BAMB31 to
BAMB0
11.2.6

Break Data Register B (BDRB)

BDRB is a 32-bit readable/writable register. The control bits CDB1, CDB0, XYE, and XYS in
BBRB select one of the four data buses for break condition B.
Bit Bit Name
31 to 0 BDB31 to
BDB0
Initial
Value R/W Description
All 0 R/W Break Address Mask B
Specify bits masked in the break address of channel B
specified by BARB (BAB31 to BAB0).
0: Break address BABn of channel B is included in the
1: Break address BABn of channel B is masked and is
Note: n = 31 to 0
Initial
Value R/W Description
All 0 R/W Break Data Bit B
Store data which specifies a break condition in
channel B.
If the I bus is selected in BBRB, the break data on IDB
is set in BDB31 to BDB0.
If the L bus is selected in BBRB, the break data on
LDB is set in BDB31 to BDB0.
If the X memory is selected in BBRB, the break data in
bits 15 to 0 in XDB is set in BDB31 to BDB16. In this
case, the values in BDB15 to BDB0 are arbitrary.
If the Y memory is selected in BBRB, the break data in
bits 15 to 0 in YDB are set in BDB15 to BDB0. In this
case, the values in BDB31 to BDB16 are arbitrary.
Section 11 User Break Controller (UBC)
break condition
not included in the break condition
Rev. 4.00 Sep. 14, 2005 Page 247 of 982
REJ09B0023-0400