Renesas HD6417641 Hardware Manual page 130

Section 2 CPU
Instruction
STC R7_BANK,Rn
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
STC.L SSR,@–Rn
STC.L SPC,@–Rn
STC.L R0_BANK,
@–Rn
STC.L R1_BANK,
@–Rn
STC.L R2_BANK,
@–Rn
STC.L R3_BANK,
@–Rn
STC.L R4_BANK,
@–Rn
STC.L R5_BANK,
@–Rn
STC.L R6_BANK,
@–Rn
STC.L R7_BANK,
@–Rn
STS MACH,Rn
STS MACL,Rn
STS PR,Rn
STS.L MACH,@–Rn
STS.L MACL,@–Rn
STS.L PR,@–Rn
TRAPA #imm
Note: Number of states before the chip enters the sleep state.
*
The table shows the minimum number of clocks required for execution. In practice, the
number of execution cycles will be increased if there is contention between an
instruction fetch and a data access, or if the destination register of a load instruction
(memory → register) is also used by the following instruction.
Rev. 4.00 Sep. 14, 2005 Page 80 of 982
REJ09B0023-0400
Instruction Code
0000nnnn11110010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0100nnnn00110011
0100nnnn01000011
0100nnnn10000011
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Operation
R7_BANK→ Rn
Rn–4 → Rn, SR → (Rn)
Rn–4 → Rn, GBR → (Rn)
Rn–4 → Rn, VBR → (Rn)
Rn–4 → Rn, SSR → (Rn)
Rn–4 → Rn, SPC → (Rn)
Rn–4 → Rn, R0_BANK → (Rn)
Rn–4 → Rn, R1_BANK → (Rn)
Rn–4 → Rn, R2_BANK → (Rn)
Rn–4 → Rn, R3_BANK → (Rn)
Rn–4 → Rn, R4_BANK → (Rn)
Rn–4 → Rn, R5_BANK → (Rn)
Rn–4 → Rn, R6_BANK → (Rn)
Rn–4 → Rn, R7_BANK → (Rn)
MACH → Rn
MACL → Rn
PR → Rn
Rn–4 → Rn, MACH → (Rn)
Rn–4 → Rn, MACL → (Rn)
Rn–4 → Rn, PR → (Rn)
PC → SPC, SR → SSR,
imm << 2 → TRA,
VBR + H'0100 → PC
Execution
States T Bit
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
1 —
8 —