Table 12.21 Minimum Number Of Idle Cycles Between Access Cycles Of Cpu And The Dmac Dual Address Mode For The Sdram Interface - Renesas HD6417641 Hardware Manual

Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC
Dual Address Mode for the SDRAM Interface
BSC Register Setting
CSnBCR CS3WCR.
Idle WTRP
Setting Setting
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
0 2
0 2
0 2
0 2
0 3
0 3
0 3
0 3
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
1 2
1 2
1 2
CS3WCR.
TRWL Read to
Setting Read
0 1/1/1/2
1 1/1/1/2
2 1/1/1/2
3 1/1/1/2
0 2/2/2/2
1 2/2/2/2
2 2/2/2/2
3 2/2/2/2
0 3/3/3/3
1 3/3/3/3
2 3/3/3/3
3 3/3/3/3
0 4/4/4/4
1 4/4/4/4
2 4/4/4/4
3 4/4/4/4
0 2/2/2/2
1 2/2/2/2
2 2/2/2/2
3 2/2/2/2
0 2/2/2/2
1 2/2/2/2
2 2/2/2/2
3 2/2/2/2
0 3/3/3/3
1 3/3/3/3
2 3/3/3/3
Section 12 Bus State Controller (BSC)
CPU Access
Write to Read to
Write Write
1/1/2/3 3/3/4/5
1/1/2/3 3/3/4/5
2/2/2/3 3/3/4/5
3/3/3/3 3/3/4/5
1/1/2/3 3/3/4/5
2/2/2/3 3/3/4/5
3/3/3/3 3/3/4/5
4/4/4/4 3/3/4/5
2/2/2/3 3/3/4/5
3/3/3/3 3/3/4/5
4/4/4/4 3/3/4/5
5/5/5/5 3/3/4/5
3/3/3/3 4/4/4/5
4/4/4/4 4/4/4/5
5/5/5/5 4/4/4/5
6/6/6/6 4/4/4/5
1/1/2/3 3/3/4/5
1/1/2/3 3/3/4/5
2/2/2/3 3/3/4/5
3/3/3/3 3/3/4/5
1/1/2/3 3/3/4/5
2/2/2/3 3/3/4/5
3/3/3/3 3/3/4/5
4/4/4/4 3/3/4/5
2/2/2/3 3/3/4/5
3/3/3/3 3/3/4/5
4/4/4/4 3/3/4/5
Rev. 4.00 Sep. 14, 2005 Page 393 of 982
DMAC Access
Write to Read to
Read Write
0/0/0/0 2
1/1/1/1 2
2/2/2/2 2
3/3/3/3 2
1/1/1/1 2
2/2/2/2 2
3/3/3/3 2
4/4/4/4 2
2/2/2/2 3
3/3/3/3 3
4/4/4/4 3
5/5/5/5 3
3/3/3/3 4
4/4/4/4 4
5/5/5/5 4
6/6/6/6 4
1/1/1/1 2
1/1/1/1 2
2/2/2/2 2
3/3/3/3 2
1/1/1/1 2
2/2/2/2 2
3/3/3/3 2
4/4/4/4 2
2/2/2/2 3
3/3/3/3 3
4/4/4/4 3
REJ09B0023-0400
Write to
Read
0
1
2
3
1
2
3
4
2
3
4
5
3
4
5
6
1
1
2
3
1
2
3
4
2
3
4