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Data Array Read: The data specified by L (bits 3 and 2) in the address is read from the entry
address specified by the address and the entry corresponding to the way.
Data Array Write: The longword data specified by the data is written to the position specified by
L (bits 3 and 2) in the address from the entry address specified by the address and the entry
corresponding to the way.
1.
Address array access
(a) Address specification
Read access
31
1111 0000
Write access
31
1111 0000
(b) Data specification (both read and write accesses)
31 30 29
0
0
0
2.
Data array access (both read and write accesses)
(a) Address specification
31
1111 0001
(b) Data specification
31
[Legend]
*:
Don't care bit
X:
0 for read, don't care for write
Figure 7.4 Specifying Address and Data for Memory-Mapped Cache Access
24
23
14
* ............ *
24
23
14
* ............ *
Address tag (28 to 10)
24
23
14
* ............ *
13
12
11
W
Entry
13
12
11
W
Entry
10
9
LRU
13
12
11
W
Entry
Longword
Rev. 4.00 Sep. 14, 2005 Page 191 of 982
Section 7 Cache
4
3
2
0
0
0
4
3
2
A
0
0
4
3
2
1
X
X
U
4
3
2
1
L
0
REJ09B0023-0400
0
0
0
0
0
V
0
0
0
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