Renesas HD6417641 Hardware Manual page 124

Section 2 CPU
Instruction
DMULU.L Rm,Rn
DT Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
MAC.L @Rm+,@Rn+
MAC.W @Rm+,@Rn+
MUL.L Rm,Rn
MULS.W Rm,Rn
MULU.W Rm,Rn
NEG Rm,Rn
NEGC Rm,Rn
SUB Rm,Rn
SUBC Rm,Rn
Rev. 4.00 Sep. 14, 2005 Page 74 of 982
REJ09B0023-0400
Instruction Code
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
Operation
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 4 bits
Rn – 1 → Rn, if Rn = 0, 1
→ T, else 0 → T
A byte in Rm is sign-extended
→ Rn
A word in Rm is sign-extended
→ Rn
A byte in Rm is zero-extended
→ Rn
A word in Rm is zero-extended
→ Rn
Signed operation of (Rn)
× (Rm) → MAC → MAC,
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
Signed operation of (Rn)
× (Rm) → MAC → MAC,
Rn + 2 → Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
Rn × Rm → MACL
32 × 32 → 32 bits
Signed operation of
Rn × Rm → MAC
16 × 16 → 32 bits
Unsigned operation of
Rn × Rm → MAC
16 × 16 → 32 bits
0–Rm → Rn
0–Rm–T → Rn,
Borrow → T
Rn–Rm → Rn
Rn–Rm–T → Rn,
Borrow → T
Execution
States T Bit
1
2(5) * —
1 Comparison
result
1 —
1 —
1 —
1 —
1
2(5)* —
1
2(5)* —
1
2(5)* —
2
1(3)* —
2
1(3)* —
1 —
1 Borrow
1 —
1 Borrow