Figure 19.1 Block Diagram Of Scif - Renesas HD6417641 Hardware Manual

SCFRDR
(16 stage)
RxD
SCRSR
TxD
SCK
CTS
RTS
[Legend]
SCRSR: Receive shift register
SCFRDR: Receive FIFO data register
SCTSR:
Transmit shift register
SCFTDR: Transmit FIFO data register
SCSMR: Serial mode register
SCSCR: Serial control register
Section 19 Serial Communication Interface with FIFO (SCIF)
Module data bus
SCSMR
SCFTDR
SCLSR
(16 stage)
SCFDR
SCFCR
SCFSR
SCTSR
SCSCR
SCSPTR
Transmission/
reception
control
Parity generation
Parity check
SCFSR:
Serial status register
SCBRR:
Bit rate register
SCSPTR:
Serial port register
SCFCR:
FIFO control register
SCFDR:
FIFO data count register
SCLSR: Line status register

Figure 19.1 Block Diagram of SCIF

SCBRRn
Baud rate
generator
Clock
External clock
SCIF
Rev. 4.00 Sep. 14, 2005 Page 687 of 982
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
BRI
REJ09B0023-0400