Figure 12.13 Access Timing For Mpx Space (Address Cycle Wait 1, Data Cycle No Wait) - Renesas HD6417641 Hardware Manual

CKIO
A25 to A16
CSn
RD/WR
Read
D7 to D0 or
D15 to D0
WEn
Write
D7 to D0 or
D15 to D0
DACKn*

Figure 12.13 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait)

Ta1 Tadw
AH
RD
BS
Note: * The waveform for DACKn is when active low is specified.
Section 12 Bus State Controller (BSC)
Ta2 Ta3
Address
Address
Rev. 4.00 Sep. 14, 2005 Page 333 of 982
T1 T2
Data
Data
REJ09B0023-0400