Renesas HD6417641 Hardware Manual page 974

Section 25 Electrical Characteristics
Item
Write data delay time 1
Write data delay time 2
Write data delay time 3
Write enable hold time 1
Write enable hold time 2
Write enable hold time 3
WAIT setup time 1
WAIT setup time 2
WAIT hold time 1
WAIT hold time 2
RAS delay time 1
RAS delay time 2
CAS delay time 1
CAS delay time 2
DQM delay time 1
DQM delay time 2
CKE delay time 1
CKE delay time 2
AH delay time
Multiplexed address delay time t
Multiplexed address hold time
DACK, TEND delay time
FRAME delay time
Note: * The maximum value (f
cycles and the system configuration of your board.
Rev. 4.00 Sep. 14, 2005 Page 924 of 982
REJ09B0023-0400
Bφ = 50 MHz*
Symbol Min.
t —
WDD1
t —
WDD2
t —
WDD3
t 1
WDH1
t 1
WDH2
t 1/2t
WDH3 cyc
t 1/2t + 8
WTS1 cyc
t 8
WTS2
t 1/2t + 4
WTH1 cyc
t 4
WTH2
t 1
RASD1
t 1/2t
RASD2 cyc
t 1
CASD1
t 1/2t
CASD2 cyc
t 1
DQMD1
t 1/2t
DQMD2 cyc
t 1
CKED1
t 1/2t
CKED2 cyc
t 1/2t
AHD cyc
—
MAD
t 0
MAH
t —
DACD
t 1
FMD
) of Bφ (external bus clock) depends on the number of wait
max
Max. Unit
14 ns
14 ns
1/2t + 14 ns
cyc
— ns
— ns
— ns
— ns
— ns
— ns
— ns
12 ns
1/2t + 12 ns
cyc
12 ns
1/2t + 12 ns
cyc
12 ns
1/2t + 12 ns
cyc
12 ns
1/2t + 12 ns
cyc
1/2t + 12 ns
cyc
12 ns
— ns
ns
Refer to
peripheral modules
12 ns
Figure(s)
25.13 to 25.21
25.27 to 25.30,
25.34 to 25.36
25.40
25.13 to 25.21
25.27 to 25.30,
25.34 to 25.36
25.40
25.14, 25.15,
25.17 to 25.22
25.16
25.14, 25.15,
25.17 to 25.22
25.16
25.23 to 25.34,
25.36 to 25.39
25.40, 25.41
25.23 to 25.39
25.40, 25.41
25.23 to 25.36
25.40, 25.41
25.38
25.41
25.18
25.18
25.18
25.13 to 25.34
25.19