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Section 2 CPU
System Control Instructions
Table 2.24 System Control Instructions
Instruction
CLRMAC
CLRS
CLRT
LDC
Rm,SR
LDC
Rm,GBR
LDC
Rm,VBR
LDC
Rm,SSR
LDC
Rm,SPC
LDC
Rm,R0_BANK
LDC
Rm,R1_BANK
LDC
Rm,R2_BANK
LDC
Rm,R3_BANK
LDC
Rm,R4_BANK
LDC
Rm,R5_BANK
LDC
Rm,R6_BANK
LDC
Rm,R7_BANK
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDC.L @Rm+,SSR
LDC.L @Rm+,SPC
LDC.L @Rm+,
R0_BANK
LDC.L @Rm+,
R1_BANK
LDC.L @Rm+,
R2_BANK
LDC.L @Rm+,
R3_BANK
Rev. 4.00 Sep. 14, 2005 Page 78 of 982
REJ09B0023-0400
Instruction Code
0000000000101000
0000000001001000
0000000000001000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00111110
0100mmmm01001110
0100mmmm10001110
0100mmmm10011110
0100mmmm10101110
0100mmmm10111110
0100mmmm11001110
0100mmmm11011110
0100mmmm11101110
0100mmmm11111110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00110111
0100mmmm01000111
0100mmmm10000111
0100mmmm10010111
0100mmmm10100111
0100mmmm10110111
Operation
0 → MACH, MACL
0 → S
0 → T
Rm → SR
Rm → GBR
Rm → VBR
Rm → SSR
Rm → SPC
Rm → R0_BANK
Rm → R1_BANK
Rm → R2_BANK
Rm → R3_BANK
Rm → R4_BANK
Rm → R5_BANK
Rm → R6_BANK
Rm → R7_BANK
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
(Rm) → SSR, Rm + 4 → Rm
(Rm) → SPC, Rm + 4 → Rm
(Rm) → R0_BANK,
Rm + 4 → Rm
(Rm) → R1_BANK,
Rm + 4 → Rm
(Rm) → R2_BANK,
Rm + 4 → Rm
(Rm) → R3_BANK,
Rm + 4 → Rm
Execution
States
T Bit
1
—
1
—
1
0
6
LSB
4
—
4
—
4
—
4
—
4
—
4
—
4
—
4
—
4
—
1
—
4
—
4
—
8
LSB
4
—
4
—
4
—
4
—
4
—
4
—
4
—
4
—
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