Table 3.18 Summary Of Dsp Data Transfer Instructions - Renesas HD6417641 Hardware Manual

Table 3.18 Summary of DSP Data Transfer Instructions

Address registers
Index register(s)
Addressing
operations
Modulo addressing
Data bus
Data length
Bus conflict
Memory
Source registers
Destination registers Dx: X0/X1, Dy: Y0/Y1
Addressing for MOVX.W and MOV.W: This LSI can access X and Y data memories
simultaneously (MOVX.W and MOVY.W). The DSP instructions have two address pointers that
simultaneously access X and Y data memories. The DSP instruction has only pointer-addressing
(it does not have immediate-addressing). Address registers are divided into two sets, R4 and R5
(Ax: Address register for X memory) and R6 and R7 (Ay: Address register for Y memory). There
are three data addressing types for X and Y data transfer instructions.
1. Not-update address register
2. Add-index register
3. Increment address register
Each address pointer set has an index register, R8[Ix] for set Ax, and R9[Iy] for set Ay. Address
instructions for set Ax use ALU in the CPU, and address instructions for set Ay use a different
address unit (figure 3.19).
X and Y Data Transfer
Operation (MOVX.W and
MOVY.W)
Ax: R4 and R5, Ay: R6 and R7
Ix: R8, Iy: R9
Not update/Increment (+2)/
Add-index-register
Post-update
Yes
XDB and YDB
16 bits (word)
No
X and Y data memories
Dx, Dy: A0 and A1
Section 3 DSP Operation
Single Data Transfer Operation
(MOVS.W and MOVS.L)
As: R2, R3, R4 and R5
Is: R8
Not update/Increment (+2)/
Add-index-register
Post-update
Decrement (–2, –4): Pre-update
No
LDB
16 bits/32 bits (word/longword)
Possible (same as the SH)
All memory spaces
DS: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G,
A1G
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G,
A1G
Rev. 4.00 Sep. 14, 2005 Page 133 of 982
REJ09B0023-0400