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Section 4 Clock Pulse Generator (CPG)
4.2
Input/Output Pins
Table 4.1 lists the CPG pins and their functions.
Table 4.1
Pin Configuration and Functions of the Clock Pulse Generator
Pin Name
Mode control pins
Crystal input/output pins
(Clock input pins)
Clock input/output pin
Clock-output pin
4.3
Clock Operating Modes
Table 4.2 shows the relationship between the mode control pins (MD2 and MD0) combinations
and the clock operating modes. Table 4.3 shows the usable frequency ranges in the clock operating
modes.
Table 4.2
Clock Operating Modes
Pin Values
Mode
MD2
MD0
2
0
0
6
1
0
7
1
1
Rev. 4.00 Sep. 14, 2005 Page 146 of 982
REJ09B0023-0400
Function
Symbol I/O
(clock operating modes 2 and 6)
MD0
Input
Set the clock operating mode.
MD2
Input
Set the clock operating mode.
XTAL
Output Connected to the crystal resonator (leave this pin open-circuit
when the crystal resonator is not in use).
EXTAL
Input
Connected to the crystal resonator or used to input an external
clock.
CKIO
I/O
Clock output pin. The pin can also
be placed in the high-impedance
state.
CKIO2
Output Low-level output or clock output pin.
The selection is described in the
description of the common control
registers in section 12, Bus State
Controller (BSC).
Clock I/O
Source
Output
EXTAL or
CKIO
Crystal resonator
EXTAL or
CKIO
Crystal resonator
CKIO
PLL2
PLL1
On/Off
On/Off
ON (×4)
ON (×1, 2)
ON (×2)
ON (×1, 2, 3, 4)
OFF
ON (×1, 2, 3, 4)
Function
(clock operating mode 7)
Input for the external clock
pulse.
High impedance
CKIO Frequency
(EXTAL or
Crystal resonator) ×4
(EXTAL or
Crystal resonator) ×2
(CKIO)
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