Clocked Synchronous Serial Format; Figure 16.12 Slave Receive Mode Operation Timing (2); Figure 16.13 Clocked Synchronous Serial Transfer Format - Renesas HD6417641 Hardware Manual

SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
RDRF
ICDRS
ICDRR
User
processing

Figure 16.12 Slave Receive Mode Operation Timing (2)

16.4.6

Clocked Synchronous Serial Format

This module can be operated with the clocked synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
Data Transfer Format:
Figure 16.13 shows the clocked synchronous serial transfer format.
The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.

Figure 16.13 Clocked Synchronous Serial Transfer Format

9 1 2 3
Bit 7 Bit 6 Bit 5
A
Data 1
SCL
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
SDA
Section 16 I
4 5 6 7
Bit 4 Bit 3 Bit 2 Bit 1
[3] Set ACKBT
Bit 5 Bit 6
Rev. 4.00 Sep. 14, 2005 Page 497 of 982
2
C Bus Interface 2 (IIC2)
8 9
Bit 0
A
Data 2
Data 1
[3] Read ICDRR [4] Read ICDRR
Bit 7
REJ09B0023-0400