Table of Contents
Advertisement
Section 2 CPU
Table 2.27 Single Data Transfer Instructions
Instruction
MOVS.W @-As,Ds
MOVS.W @As,Ds
MOVS.W @As+,Ds
MOVS.W @As+Is,Ds
MOVS.W Ds,@-As*
MOVS.W Ds,@As*
MOVS.W Ds,@As+*
MOVS.W Ds,@As+Is* 111101AADDDD1101
MOVS.L @-As,Ds
MOVS.L @As,Ds
MOVS.L @As+,Ds
MOVS.L @As+Is,Ds
MOVS.L Ds,@-As
MOVS.L Ds,@As
MOVS.L Ds,@As+
MOVS.L Ds,@As+Is
Note:
If guard bit registers A0G and A1G are specified in source operand Ds, the data is
*
output to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8].
Rev. 4.00 Sep. 14, 2005 Page 86 of 982
REJ09B0023-0400
Instruction Code
111101AADDDD0000
111101AADDDD0100
111101AADDDD1000
111101AADDDD1100
111101AADDDD0001
111101AADDDD0101
111101AADDDD1001
111101AADDDD0010
111101AADDDD0110
111101AADDDD1010
111101AADDDD1110
111101AADDDD0011
111101AADDDD0111
111101AADDDD1011
111101AADDDD1111
Operation
As – 2 → As, (As) →
MSW of Ds, 0 → LSW of Ds
(As) → MSW of Ds,
0 → LSW of Ds
(As) → MSW of Ds,
0 → LSW of Ds, As + 2 → As
(Asc) → MSW of Ds,
0 → LSW of Ds, As + Is → As
As – 2 → As,
MSW of Ds → (As)
MSW of Ds → (As)
MSW of Ds → (As),
As + 2 → As
MSW of Ds → (As),
As + Is → As
As – 4 → As, (As) → Ds
(As) → Ds
(As) → Ds, As + 4 → As
(As) → Ds, As + Is → As
As – 4 → As, Ds → (As)
Ds → (As)
Ds → (As), As + 4 → As
Ds → (As), As + Is → As
Execution
States
DC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Advertisement
Table of Contents
